Real-time iris segmentation and its implementation on FPGA

Abstract

This paper presents a real-time iris segmentation technique that is well suited to a fast implementation on an FPGA. One major hurdle associated with iris segmentation techniques is the use of iterative processes that lead to expensive hardware implementations. To circumvent this, the proposed algorithm uses the sign image obtained from subtracting the background, along with morphological operators to localise the pupil. The outer boundary is located by first normalising a selected image region that contains the iris, and then using a first-order gradient operator. The proposed non-iterative algorithm is implemented on an FPGA. Four near infrared (NIR) iris public databases, namely: CASIA-IrisV3-Lamp, MMU v1.0, ND-IRIS-0405 and NIST ICE 2005, are used to test the proposed algorithm. The proposed method for iris segmentation and normalization gives much better accuracy than the existing state-of-the-art methods implemented on hardware. The proposed realisation requires about 45% fewer logic registers and 52% fewer logic elements than the existing state-of-the-art implementations.

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